EPRO PR9376010-011軸位移探頭
對于多功能設(shè)備，所有功能都可以使用相同的INTx#線，或者每個功能都可以有自己的（最多四個功能），或者它們的任意組合。單個函數(shù)永遠(yuǎn)不能在多條INTx#線上生成中斷請求。從PIC通過BIOS定義的線路接受VME中斷。BIOS根據(jù)哪個系統(tǒng)需要使用中斷線來定義要使用的中斷線。PCI設(shè)備中斷圖基于PCI總線的外部設(shè)備包括PMC站點、以太網(wǎng)控制器和PCI到VME橋。默認(rèn)BIOS將這些外部設(shè)備映射到ICH2的PCI中斷請求（PIRQx）線路。該映射如第47頁圖2-1所示，定義見表2-5。無法修改每個設(shè)備上的設(shè)備PCI中斷線（INTA到INTD）。PCI到VME橋具有通過PCI SERR#線生成非屏蔽中斷（NMI）的能力。表2-6描述了NMI使用的寄存器位。SERR中斷通過邏輯路由回CPU上的NMI輸入線。CPU讀取NMI狀態(tài)控制寄存器以確定NMI源（位設(shè)置為1）
For a
multifunction device, all functions may use the same INTx# line, or each may have its
own (up to a maximum of four functions), or any combination thereof. A single
function can never generate an interrupt request on more than one INTx# line.The slave PIC accepts the VME interrupts through lines that are defined by the BIOS.
The BIOS defines which interrupt line to utilize depending on which system requires
the use of the line.
PCI Device Interrupt Map
The PCI bus-based external devices include the PMC sites, Ethernet controller and the
PCI-to-VME bridge. The default BIOS maps these external devices to the PCI
Interrupt Request (PIRQx) lines of the ICH2. This mapping is illustrated in Figure 2-1
on page 47 and is defined in Table 2-5.
The device PCI interrupt lines (INTA through INTD) that are present on each device
cannot be modified.The PCI-to-VME Bridge has the capability of generating a Non-Maskable Interrupt
(NMI) via the PCI SERR# line. Table 2-6 describes the register bits that are used by the
NMI. The SERR interrupt is routed through logic back to the NMI input line on the
CPU. The CPU reads the NMI Status Control register to determine the NMI source
(bits set to 1)
